Logic-timing Simulation and the Degradation Delay ModelThis book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the OC Degradation Delay ModelOCO, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications." |
Contents
1 Fundamentals of Timing Simulation | 1 |
Evolution and Trends | 23 |
3 Degradation and Inertial Effects | 47 |
4 CMOS Inverter Degradation Delay Model | 75 |
5 GateLevel DDM | 127 |
6 Logic Level Simulator Design and Implementation | 181 |
7 DDM Simulation Results | 203 |
8 Accurate Measurement of the Switching Activity | 227 |
251 | |
265 | |
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Common terms and phrases
accurate analysis applied approach basic behaviour calculate called capacitance cell chapter characteristics characterization characterization process circuit CMOS inverter collisions complex considered corresponding curves defined degradation effect degradation parameters delay models dependence described devices dynamic electrical simulation element equations error et al example expressions falling fitting frequency function gate level given glitches HALOTIS hand HSPICE implemented important input transition load logic simulation maximum means measuring method necessary netlist node objective obtained operation oscillation output transition possible precision presented produce propagation delay proposed pulse range reach region relative represents respect rising sensitivity shown shows signals simplified slope specified switching activity Table tasks threshold tion transistor typical variations verification Verilog voltage width