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" A. Nabavi-Lishi and NC Rumin, "Inverter Models of CMOS Gates for Supply Current and Delay Evaluation", IEEE Trans. "
Logic-timing Simulation and the Degradation Delay Model - Page 259
by Manuel J. Bellido, Jorge Juan Chico, Manuel Valencia - 2006 - 267 pages
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Field-Programmable Logic and Applications. From FPGAs to Computing Paradigm ...

Reiner W. Hartenstein, Andres Keevallik - Computers - 1998 - 808 pages
...delay and other formulas”, IEEE JSSC vol. 25, pp 584-594, April 1990. 5. A. Nabavi_Lishi, NC Rumin “Inverter models of CMOS gates for supply current and delay evaluation”, IEEE trans. On CAD of Integrated Circuits and systems, vol.13, n°10, pp.1271-1279, 1994. 6. KO Jeppson,...
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Memory, Microprocessor, and ASIC

Wai-Kai Chen - Technology & Engineering - 2003 - 386 pages
...CMOS inverters, IEEE Trans. Circuits. Syst, 39(1), 42-45, Jan. 1992. 15. A. Nabavi-Lishi and NC Rumin, Inverter models of CMOS gates for supply current and delay evaluation, IEEE Trans. Computer-Aided Design, 13(10), 1271-1279, Oct. 1994. 16. J. Rubinstein, P. Penfield, and MA...
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