Logic-timing Simulation and the Degradation Delay ModelThis book provides the reader with an extensive background in the field of logic-timing simulation and delay modeling. It includes detailed information on the challenges of logic-timing simulation, applications, advantages and drawbacks. The capabilities of logic-timing are explored using the latest research results that are brought together from previously disseminated materials. An important part of the book is devoted to the description of the ?Degradation Delay Model?, developed by the authors, showing how the inclusion of dynamic effects in the modeling of delays greatly improves the application cases and accuracy of logic-timing simulation. These ideas are supported by simulation results extracted from a wide range of practical applications.Sample Chapter(s) |
What people are saying - Write a review
We haven't found any reviews in the usual places.
Contents
Fundamentals of Timing Simulation | 1 |
Delay Models Evolution and Trends | 23 |
Degradation and Inertial Effects | 47 |
CMOS Inverter Degradation Delay Model | 75 |
GateLevel DDM | 127 |
Logic Level Simulator Design and Implementation | 181 |
DDM Simulation Results | 203 |
Accurate Measurement of the Switching Activity | 227 |
Other editions - View all
Common terms and phrases
accurate algorithm basic model behavioural model calculate capacitance cell library chapter characterization process CMOS gates CMOS inverter complex considered corresponding curves Daga degra degradation effect degradation parameters Delay calculation delay models delay value dependence digital circuits dynamic electrical simulation equations example expressions frequency function gate level glitches HALOTIS HSPICE implemented inertial delay inertial effect input collisions input pulse input transition IOCC linear logic gate logic simulation maximum measuring metastability MOSFET netlist NMOS node normal propagation delay number of inputs number of transitions operation oscillation out2 output load overshoot PMOS post-layout precision region relative error respect ring oscillator sensitivity shown in Fig shows signals simplified model slope static stimuli submicron switching activity Table threshold tion transient analysis transistor level Type 2 collisions types of simulation typical value Value Error vectors verification Verilog waveform width
Popular passages
Page 252 - A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in FORTRAN,
Page 259 - A. Nabavi-Lishi and NC Rumin, "Inverter Models of CMOS Gates for Supply Current and Delay Evaluation", IEEE Trans.
Page 261 - ILLIADS: A fast timing and reliability simulator for digital MOS circuits,
Page 257 - An accurate and efficient delay time modeling for MOS logic circuits using polynomial approximation,
Page 252 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 1, No. 2, 1993, pp 191-202. [12] Michael Weeks, Magdy Bayoumi, "3-D Discrete Wavelet Transform Architectures, " IEEE Int. Symposium on Circuits and Systems (ISCAS "98), Monterey, California, May 31 - June 3. 1998. [13] G. Knowles, "VLSI Architecture for the Discrete Wavelet Transform...
Page 257 - IEEE Transactions on Circuits and Systems-I: Fundamental Theory and Applications, vol. 39, no. 5, pp. 351 - 364, May 1992. [3] YH Hu and D.-J. Wang, "An efficient multiprcessor implementation scheme for real-time DSP algorithms," in Fourth Great Lakes Symposium on VLSI, pp.
Bibliographic information
| Title | Logic-timing Simulation and the Degradation Delay Model EngineeringPro collection |
| Authors | Manuel J. Bellido, Jorge Juan Chico, Manuel Valencia |
| Edition | illustrated |
| Publisher | Imperial College Press, 2006 |
| ISBN | 1860945899, 9781860945892 |
| Length | 267 pages |
| Subjects | › Computers / Computer Engineering Technology & Engineering / Electrical |
| Export Citation | BiBTeX EndNote RefMan |